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wait state
Last modified: Tuesday, October 30, 2001 

A time-out period during which a CPU or bus lies idle. Wait states are sometimes required because different components function at different clock speeds. For example, if the CPU is much faster than the memory chips, it may need to sit idle during some clock cycles so that the memory chips can catch up. Likewise, buses sometimes require wait states if expansion boards run slower than the bus.

A zero wait state system is one in which the microprocessor runs at the maximum speed without any time-outs to compensate for slow memory. Wait states can be avoided by using a variety of techniques, including page-mode memory, interleaved memory, a burst mode, and memory caches.

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related categories

Microprocessors

Performance

related terms

burst mode

cache

clock speed

FPM RAM

interleave

latency

oscillator clock

pipeline burst cache

RAM latency

SDRAM

system bus


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